1. Field of the Invention
The present invention relates to comparators, and more specifically to a method and apparatus for comparing two differential signals while consuming low power.
2. Related Art
Comparators are often used to compare two input signals. A typical comparator compares two input signals and generates an output signal representing the comparison result. The input and output signals can be either single ended or differential as is well known in the relevant arts. A single ended signal commonly refers to a signal which uses ground level (or zero voltage) as a reference.
On the other hand, a differential signal is represented by two single ended signals, with the strength (e.g., voltage level) of the differential signal equaling the difference of the two single ended signals. By using the difference, any common noise in the two signals may be eliminated as is well known in the relevant arts.
In one prior embodiment, two differential signals are provided as inputs to a double differential amplifier modeled as having infinite (or high) gain, the output swings to + or xe2x88x92 voltage level depending on the result of the comparison. Unfortunately, high gain amplifiers typically consume excessive electrical power and are unsuitable in several environments. For example, a charged coupled capacitor (CCD) camera may need to consume minimal power and yet need comparators within.
In an alternative prior embodiment, an amplifier with a relatively low gain (e.g., a gain of 10) is employed. Due to the low gain, the output of the amplifier reflects the result of the comparison, but may not have a desired level of voltage. For example, the voltage level may need to equal a logical level (e.g., 3 Volts) of a binary bit. The desired amplification may be achieved by providing the input to a regenerative latch which amplifies the signal. The signal is amplified in a short duration to the desired level due to the internal positive feedback.
One problem with such an alternative embodiment is that the input offset of the amplifier may be unacceptably high. An input offset generally refers to minimum voltage level difference that needs to be present between the two inputs for a comparison operation to be accurate. Ideally, the input offset should equal zero volts.
However, a lower input offset typically requires high power consumption as is well known in the relevant arts. As noted above, high power consumption is undesirable in several environments. Therefore, what is needed is a method and an apparatus for comparisons of two differential signals while minimizing offset and power.
A comparator provided in accordance with the present invention compares an input differential signal (represented by single-ended signals INP and INM) with a reference differential signal (represented by single-ended signals REFP or REFM), and generates a comparison result at a desired higher voltage level. A single ended signal (INP or INM) of the input differential signal is averaged with another single-ended signal (REFP or REFM) of the reference signal to generate a first average signal.
The remaining two single-ended signals (one each from the input differential signal and the reference differential signal) may also be averaged to generate a second average signal. The difference of the two averages may be amplified to generate the comparison result at the desired higher voltage level. To keep the averages within a low voltage range, each average is generated based on one positive single ended signal and a negative single ended signal.
In one embodiment, the comparator contains two regenerative latches. The first regenerative latch is coupled between a first node and a second node. The second regenerative latch is coupled between a third node and a fourth node. The first node is connected to the third node by a first xcfx86Z switch and the second node is connected to the fourth node by a second xcfx86Z switch.
The first regenerative latch is enabled and disabled according to a first xcfx86ZD switch and the second regenerative latch is enabled and disabled according to a second xcfx86ZD switch. Each of the four nodes may contain a parasitic capacitance (of a capacitor), which may be modeled as a capacitance connected to the ground. The first, second, third and fourth nodes may respectively be connected to the REFP, INP, INM and REFM signals via a first, second, third and fourth xcfx86 switches.
In operation, the four xcfx86 switches are closed during a sample phase to cause the four capacitors to be charged by a voltage level provided on the corresponding one of the INP, INM. REFM, and REFP signals. Then, during an average phase, the four xcfx86 switches may be opened and the first xcfx86Z switch may be closed to cause the voltages across the first node and the second node to be averaged to generate a first average voltage. The second xcfx86Z switch also may also be closed during the average phase to cause the voltages across the second node and the fourth node to be averaged to generate a second average voltage. In an embodiment, the parasitic capacitance of the first node is designed equal to that of the third node, and the parasitic capacitance of the second node is designed to equal that of the fourth node.
The first and second xcfx86ZD switches are closed during a hold phase to cause the regenerative latches to generate a difference of the first average voltage and the second average voltage. In addition, the regenerative latches amplify the difference to generate an output signal representing the result of comparison of the differential input signal and the differential reference signal. The result may be amplified to generate a voltage level representing a logic state of a binary bit. The xcfx86Z switches also may be kept at least for a short duration during the hold phase such that the latches are connected in parallel in the hold phase.
In one embodiment, each latch contains a first amplifying element and a second amplifying element connected back-to-back. The two amplifying elements are enabled and disabled by one of the xcfx86ZD switches. When enabled, the amplifying elements amplify the input signals due to the positive feedback. The amplifying elements may be implemented using logic gates such as inverter, NOR, NAND, XOR, XNOR, etc., also as is well known in the relevant arts.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.